1. Field of the Invention
The present invention generally relates to analog to digital converters. More particularly, the present invention relates to a method and an apparatus for error correction in pipeline analog to digital converter architecture.
2. Description of the Related Art
Analog-to-digital (A/D) converters with pipeline architecture are well suited for low-power, high speed applications. Among the several of the currently used high conversion speed techniques such as flash, multi-step, pipeline, interpolating, and time-interleaved successive approximation, the pipeline technique offers the best trade-off between minimizing circuit complexity, silicon area, and power consumption with respect to conversion speed. Pipeline architecture can generally provide high throughput rates and occupy small die areas which are both desirable and cost efficient in A/D converters. These advantages result from the concurrent operation of each of the multiple stages in the pipeline architecture.
Broadly speaking, at any given time during the operation of the pipelined A/D converter, the first stage operates on the most recent sample inputted while subsequent stages operate on residues from the previous samples outputted from prior stages of the cascaded pipeline architecture.
In addition, a redundancy in stage bit resolution can be introduced to provide sufficiently large tolerance for non-ideal component characteristics. In particular, by providing more resolution per stage such that the sum of the individual stage resolutions is greater than the total resolution of the output digital signal, and by eliminating this redundancy with a digital correction algorithm, the effects of quantizer nonlinearity, comparator offset and incomplete settling on the overall linearity can be significantly improved.
FIG. 1 illustrates a conventional approach in determining the digital word corresponding to an analog input signal in a pipeline A/D converter architecture using 1 bit per stage. As shown, the input signal range 101 is divided into two subsection ranges 102, 103. Then, a comparator (not shown) determines into which of the two ranges 102, 103 the input signal falls, thus ascertaining the most significant bit MSB of the digital word. Upon determining the most significant bit MSB, the halved subsection range 102 containing the input signal is re-centered and amplified by two. Then, the halved subsection range 102 is again divided into two subsections 104, 105 and another comparator (not shown) determines into which half of the new subsections 104, 105 the signal falls. As can be seen from FIG. 1, the above-described steps are continuously executed. In this manner, the digital word corresponding to the analog input signal is determined one bit at a time, starting with the most significant bit MSB.
In practice, however, splitting the signal range into two results in inaccuracy due to comparator offsets, settling time errors and other errors inherent in pipeline architecture. These errors, when substantially significant, cause a wrong decision to be made at a particular stage along the pipeline architecture.
FIG. 2 illustrates the effect of the inaccuracy resulting in such errors. The solid dot indicates the location of the input signal during the various stages along a 1-bit per stage pipeline architecture. Also shown in FIG. 2 are over-range (OR) and under-range (UR) regions of the pipeline architecture.
It can be seen from FIG. 2 that the input signal at first stage 10 is close to the threshold of the first comparator (not shown) shown by the proximity of the solid dot (residing in section 203) to line 201. Due to the comparator offset, incomplete settling time or other error-causing factors as previously discussed, the comparator switches the wrong section 202 (i.e., the range which does not contain the input signal) to the second stage 20, amplified by a gain of two (2). As a result, the input signal ends up in the over-range region (OR).
Then, two types of corrections need to be carried out: analog and digital corrections. The analog correction is achieved by switching the over-range region (OR) to the third stage 30 of the pipeline architecture so that the signal is brought back into the normal range, while the digital correction is achieved by adding a "1" where the over-range condition (i.e., stage 20 of the pipeline architecture) is detected. In case of under-range condition, rather than adding a "1" as in the over-range condition, a "1" is subtracted.
For example, as shown in FIG. 2, in the first stage 10 of the pipeline architecture, each section 202, 203 between the over-range region (OR) and the under-range region (UR) corresponds to one local quantization step of the first stage 10, or two quantization steps in second stage 20 (where 1 bit equals two quantization steps). By erroneously switching section 202 from first stage 10 to second stage 20, an error results that is effectively equal to a negative quantization step (one half bit) in the first stage 10.
Generally, the errors discussed herein are relatively small in magnitude, spanning over a few least significant bits (LSBs). Therefore, error correction in the first few stages generally are not necessary, and such correction can wait until the magnitude of the error is comparable to, but less than, the local quantization step.
FIG. 3 illustrates the relative size of the error and the location of necessary error correction. As with the illustration of FIG. 2, the solid dot indicates the location of the input signal at various stages in the pipeline architecture with OR indicating the over-range region. Employing a similar amplification and subdivision of signal ranges as explained above with FIG. 2, it can be seen from FIG. 3 that the first stage 301 (not necessarily the first stage of the pipeline A/D converter architecture) makes an error that is within two local quantization steps in the fourth stage 304. In this manner, an error in the first stage 301 continues to magnify through each successive stages (stage 301 to 304) of the pipeline architecture when no error correction is implemented.
Furthermore, it can be seen from FIG. 3 that the input signal enters the over-range region at the second stage 302. If this error is directly passed onto the third stage 303, correction can still be achieved by adding a "1" at this stage (i.e., stage 303) since the input signal in the over-range region is within one local quantization step of the normal range. However, if the error is further passed onto the fourth consecutive stage 304 without correction in any of the intermediate stages (stages 302 or 303), then, the input signal is more than one local quantization step into the over-range region OR. The addition of a "1" at the fourth stage 304 in this case will not be sufficient to correct the error. Therefore, in order to implement effective error correction at stage 304, rather than adding a "1", a "2" is added at the fourth stage 304, which is equivalent to adding a "1" in the third stage 303. It is to be noted, however, that if error correction is implemented at stage 304 instead of at stage 303, a further provision is necessary to add/subtract a "1" as well as a "2" at stage 304. (A smaller error could fall within one quantization step of the normal range).
Assuming that the approach as described in FIG. 3 represents the maximum error toleration for a pipeline A/D converter architecture, in practical implementation, all stages prior to the third stage 303 can skip error correction. This is the approach suggested in Hadidi et al., "Error analysis in pipeline A/D converters and its applications", IEEE Transaction on Circuits and Systems II, vol. 39, No.8, August 1992.
According to the Hadidi approach, the location of the error correction stage along the pipeline architecture is generally determined by the maximum comparator offset and settling errors. Moreover, any other offset error resulting after the error correction stage results in an input referred error which is less than one LSB--an indication that the error is not corrected. In other words, when such errors are referred to the input signal through the interstage gains, they are, in theory, smaller than the least significant bit.
The Hadidi approach described above presents several limitations. First, it is not practically feasible to determine the comparator offset exactly prior to fabrication. Additionally, settling errors may not be sufficiently characterized. Therefore, the location of the error correction stage must be determined very conservatively. As a result, any offset error occurring after the error correction stage may not be less than one LSB when compared to the input signal. This, in turn, translates into uncorrected offset errors in the pipeline architecture which will lead to inaccuracies in analog to digital conversion.
Moreover, even if offsets beyond the error correction stage cause less than one LSB error, if these post-error correction stage offsets are uncorrected, they adversely affect the permissible differential nonlinearity (DNL) of the pipeline architecture. Also, when a single error correction stage is used as in the Hadidi approach, the additional comparators that detect over-range conditions have to be precise. Otherwise, these offsets of the over-range comparators will contribute to the existing errors (the contribution from these comparators, of course, is scaled by the interstage gains).
Additionally, as an offset error passes through the stages in the pipeline architecture without being corrected, due to the interstage gain, the signal moves further away from the normal range as shown in FIG. 3. Generally, the interstage gain blocks are designed to be linear in the normal operational range. However, the linearity of these interstage gain blocks degrades significantly as the over-range signal increases. Thus, even though the accumulated error is correctable at the chosen location for the error correction stage, there will be substantial distortion of the offset error resulting in further degradation of the differential non-linearity (DNL). Accordingly, it may be necessary to choose an error correction level which is less than one local quantization step.
Therefore, determining the location of the error correction stage from the perspective of comparator offset does not yield the optimum design when the accumulated errors push the limits of the interstage amplifiers' linearity for a given power dissipation.